Publications

(2025). GEM: GPU-Accelerated Emulator-Inspired RTL Simulation. Proceedings of the 62nd Annual Design Automation Conference (DAC) 2025.

PDF Cite Code Best Paper Nomination

(2025). INSTA: An Ultra-Fast, Differentiable, Statistical Static Timing Analysis Engine for Industrial Physical Design Applications. Proceedings of the 62nd Annual Design Automation Conference (DAC) 2025.

Cite Best Paper Award

(2025). A Systematic Approach for Multi-Objective Double-Side Clock Tree Synthesis. Proceedings of the 62nd Annual Design Automation Conference 2025.

Cite Arxiv

(2025). Addressing Continuity and Expressivity Limitations in Differentiable Physical Optimization: A Case Study in Gate Sizing. IEEE/ACM International Symposium of EDA (ISEDA) 2025.

PDF Cite Honorable Mention Paper Award

(2025). Handling Latch Loops in Timing Analysis with Improved Complexity and Divergent Loop Detection. 2025 IEEE/ACM Design, Automation and Test in Europe (DATE).

PDF Cite

(2025). PathGen: An Efficient Parallel Critical Path Generation Algorithm. IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC) 2025.

Cite DOI Best Paper Nomination

(2025). iTAP: An Incremental Task Graph Partitioner for Task-parallel Static Timing Analysis. IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC) 2025.

Cite DOI

(2024). HeteroExcept: A CPU-GPU Heterogeneous Algorithm to Accelerate Exception-aware Static Timing Analysis. IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2024.

PDF Cite DOI

(2024). HeLEM-GR: Heterogeneous Global Routing with Linearized Exponential Multiplier Method. IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2024.

PDF Cite DOI

(2024). Fusion of Global Placement and Gate Sizing with Differentiable Optimization. IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2024.

PDF Cite DOI Best Paper Nomination

(2024). PowPrediCT: Cross-Stage Power Prediction with Circuit-Transformation-Aware Learning. 61st ACM/IEEE Design Automation Conference (DAC) 2024.

PDF Cite DOI

(2024). Heterogeneous Static Timing Analysis with Advanced Delay Calculator. 2024 IEEE/ACM Design, Automation and Test in Europe (DATE).

PDF Cite DOI

(2024). Dynamic Supply Noise Aware Timing Analysis with JIT Machine Learning Integration. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

PDF Cite DOI

(2024). Analyzing Timing in Shorter Time: A Journey Through Heterogeneous Parallelism for Static Timing Analysis. 2024 IEEE 17th International Conference on Solid-State & Integrated Circuit Technology (ICSICT).

PDF Cite DOI Invited Paper

(2024). An Efficient Task-Parallel Pipeline Programming Framework. 2024 International Conference on High Performance Computing in Asia-Pacific Region (HPCAsia).

PDF Cite DOI

(2023). Accelerating Routability and Timing Optimization with Open-Source AI4EDA Dataset CircuitNet and Heterogeneous Platforms. 2023 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

PDF Cite DOI Invited Paper

(2023). General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism. 60th ACM/IEEE Design Automation Conference (DAC) 2023.

PDF Cite DOI

(2023). Accelerating Static Timing Analysis using CPU-GPU Heterogeneous Parallelism. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

PDF Cite DOI

(2023). A GPU-accelerated Framework for Path-based Timing Analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Cite DOI

(2023). DREAMPlace 4.0: Timing-driven Placement with Momentum-based Net Weighting and Lagrangian-based Refinement. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

PDF Cite DOI

(2023). Deep Learning Framework for Placement. Machine Learning Applications in Electronic Design Automation.

Cite DOI

(2023). AVATAR: An Aging-and Variation-Aware Dynamic Timing Analyzer for Error-Efficient Computing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

PDF Cite DOI

(2022). GPU-Accelerated Rectilinear Steiner Tree Generation. 2022 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

PDF Cite DOI

(2022). EventTimer: Fast and Accurate Event-Based Dynamic Timing Analysis. 2022 IEEE/ACM Design, Automation and Test in Europe (DATE).

PDF Cite DOI

(2022). Efficient Critical Paths Search Algorithm using Mergeable Heap. 27th Asia and South Pacific Design Automation Conference (ASP-DAC) 2022.

PDF Cite DOI

(2022). Differentiable-Timing-Driven Global Placement. 59th ACM/IEEE Design Automation Conference (DAC) 2022.

PDF Cite DOI

(2022). AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Application-based DVAFS. 59th ACM/IEEE Design Automation Conference (DAC) 2022.

PDF Cite DOI

(2022). A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction. 59th ACM/IEEE Design Automation Conference (DAC) 2022.

PDF Cite DOI

(2021). VAT-Mart: Learning Visual Action Trajectory Proposals for Manipulating 3D ARTiculated Objects. International Conference on Learning Representations (ICLR) 2022.

Cite Arxiv Videos

(2021). Ultrafast CPU/GPU Kernels for Density Accumulation in Placement. 58th ACM/IEEE Design Automation Conference (DAC) 2021.

PDF Cite DOI

(2021). HeteroCPPR: Accelerating Common Path Pessimism Removal with Heterogeneous CPU-GPU Parallelism. IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2021.

PDF Cite DOI

(2021). A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).

PDF Cite DOI

(2021). A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs. 58th ACM/IEEE Design Automation Conference (DAC) 2021.

PDF Cite DOI Proof Appendix

(2020). GPU-Accelerated Static Timing Analysis. IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2020.

PDF Cite Slides Video DOI