Optimizing timing is critical to the design closure of integrated circuits (IC). However, most existing algorithms for circuit placement focus on the optimization of wirelength instead of timing metrics. This paper presents a timing-driven placement framework. It consists of a global placement stage based on net weighting with momentum, and a detailed placement stage based on Lagrangian multipliers. By improving the preconditioners and timing engines to facilitate net weighting and discrete local search, we have achieved superior timing improvement on benchmarks from ICCAD 2015 contest, including worst negative slack (WNS) and total negative slack (TNS).