2

Dynamic Supply Noise Aware Timing Analysis with JIT Machine Learning Integration
The incessant decrease in transistor size has led to reduced voltage noise margins and exacerbated power integrity challenges. This …
Yufei Chen, Zizheng Guo, Runsheng Wang, Ru Huang, Yibo Lin, Cheng Zhuo
PDF Cite DOI
Accelerating Static Timing Analysis using CPU-GPU Heterogeneous Parallelism
Static timing analysis (STA) is an essential yet time-consuming task during the circuit design flow to ensure the correctness and …
Zizheng Guo, Tsung-Wei Huang, Yibo Lin
PDF Cite DOI
A GPU-accelerated Framework for Path-based Timing Analysis
As a key routine in Static Timing Analysis (STA), Path-based Analysis (PBA) plays a very important role in refining the critical path …
Guannan Guo, Tsung-Wei Huang, Yibo Lin, Zizheng Guo, Sushma Yellapragada, Martin DF Wong
Cite DOI
AVATAR: An Aging-and Variation-Aware Dynamic Timing Analyzer for Error-Efficient Computing
As the timing guardband consumes more and more design margin with the technology scaling, better-than-worst-case (BTWC) techniques have …
Zuodong Zhang, Zizheng Guo, Yibo Lin, Meng Li, Runsheng Wang, Ru Huang
PDF Cite DOI
DREAMPlace 4.0: Timing-driven Placement with Momentum-based Net Weighting and Lagrangian-based Refinement
Optimizing timing is critical to the design closure of integrated circuits (IC). However, most existing algorithms for circuit …
Peiyu Liao, Dawei Guo, Zizheng Guo, Siting Liu, Yibo Lin, Bei Yu
PDF Cite DOI
A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs
Common path pessimism removal (CPPR) is imperative for eliminating redundant pessimism during static timing analysis (STA). However, …
Zizheng Guo, Mingwei Yang, Tsung-Wei Huang, Yibo Lin
PDF Cite DOI