1 | Zizheng Guo

Addressing Continuity and Expressivity Limitations in Differentiable Physical Optimization: A Case Study in Gate Sizing

Differentiable optimization is popular for its efficiency and explainability. However, it faces limitations due to its reliance on …

Yufan Du, Zizheng Guo, Yang Hsu, Zhili Xiong, Seunggeun Kim, David Z. Pan, Runsheng Wang, Yibo Lin

Handling Latch Loops in Timing Analysis with Improved Complexity and Divergent Loop Detection

Latch loops introduce feedback cycles in timing graphs for static timing analysis (STA), disrupting timing propagation in topological …

Xizhe Shi, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang

iTAP: An Incremental Task Graph Partitioner for Task-parallel Static Timing Analysis

Recent static timing analysis (STA) tools have utilized task dependency graph (TDG) parallelism to enhance the STA runtime performance. …

Boyang Zhang, Che Chang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yang Sui, Chih-Chun Chang, Yi-Hua Chung, Wan-Luan Lee, Zizheng Guo, Yibo Lin, Tsung-Wei Huang

PathGen: An Efficient Parallel Critical Path Generation Algorithm

Critical Path Generation (CPG) is fundamental for many static timing analysis (STA) applications. As the circuit complexity continues …

Che Chang, Boyang Zhang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yi-Hua Chung, Wan-Luan Lee, Zizheng Guo, Yibo Lin, Tsung-Wei Huang

HeteroExcept: A CPU-GPU Heterogeneous Algorithm to Accelerate Exception-aware Static Timing Analysis

Static timing analysis (STA) for large-scale modern circuits requires extensive handling of false paths, multi-cycle paths, and other …

Zizheng Guo, Zuodong Zhang, Wuxi Li, Tsung-Wei Huang, Xizhe Shi, Yufan Du, Yibo Lin, Runsheng Wang, Ru Huang

Fusion of Global Placement and Gate Sizing with Differentiable Optimization

Gate sizing is critical in VLSI design because it significantly influences final design quality. Traditional design flows typically …

Yufan Du, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang

HeLEM-GR: Heterogeneous Global Routing with Linearized Exponential Multiplier Method

Add the full text or supplementary notes for the publication here using Markdown formatting.

Chunyuan Zhao, Zizheng Guo, Rui Wang, Zaiwen Wen, Yun Liang, Yibo Lin

OpenPARF 3.0: Robust Multi-Electrostatics Based FPGA Macro Placement Considering Cascaded Macros Groups and Fence Regions

FPGA macro placement strongly affects routability and timing closure, but practical constraints such as cascaded macro groups and fence …

Jing Mai, Jiarui Wang, Yifan Chen, Zizheng Guo, Xun Jiang, Yun Liang, Yibo Lin

PowPrediCT: Cross-Stage Power Prediction with Circuit-Transformation-Aware Learning

Accurate and efficient power analysis at early VLSI design stages is critical for effective power optimization. It is a promising yet …

Yufan Du, Zizheng Guo, Xun Jiang, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang

Heterogeneous Static Timing Analysis with Advanced Delay Calculator

Static timing analysis (STA) in advanced technology nodes encounter many new challenges in analysis accuracy and speed efficiency. To …

Zizheng Guo, Tsung-Wei Huang, Zhou Jin, Cheng Zhuo, Yibo Lin, Runsheng Wang, Ru Huang