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Disentangled Differentiable Timing-Power Co-Optimization with Quad-Gradient Gate Sizing

Co-optimizing timing and power in modern VLSI designs remains challenging under realistic static timing analysis and standard-cell …

Zixuan Pan, Zizheng Guo, Yufan Du, Runsheng Wang, Yibo Lin

Provably Optimal Planar Pareto Nearest Neighbor Search with Double Monotone Chains

A core task in EDA is to bridge layout and topology: given planar pins, build a sparse graph that captures who should connect to whom, …

Zizheng Guo, Runsheng Wang, Yibo Lin

HeteroSTA: A CPU-GPU Heterogeneous Static Timing Analysis Engine with Holistic Industrial Design Support

We introduce in this paper, HeteroSTA, the first CPU-GPU heterogeneous timing analysis engine that efficiently supports: (1) a set of …

Zizheng Guo, Haichuan Liu, Xizhe Shi, Shenglu Hua, Zuodong Zhang, Chunyuan Zhao, Runsheng Wang, Yibo Lin

HeteroLatch: A CPU-GPU Heterogeneous Latch-Aware Timing Analysis Engine

Latches, prevalent in high-frequency circuits, challenge timing analysis due to time borrowing and latch loops, complicating static …

Xizhe Shi, Zizheng Guo, Yibo Lin, Zuodong Zhang, Yun Liang, Runsheng Wang

IncreGPUSTA: GPU-Accelerated Incremental Static Timing Analysis for Iterative Design Flows

Static timing analysis (STA) plays an essential role in VLSI design optimization. While CPU-based incremental STA methods reduce …

Haichuan Liu, Zizheng Guo, Runsheng Wang, Yibo Lin

Differentiable Physical Optimization

Gate sizing and buffer insertion are crucial for VLSI physical optimization; however, conventional decoupled approaches often yield …

Yufan Du, Zizheng Guo, Runsheng Wang, Yibo Lin

DiffCCD: Differentiable Concurrent Clock and Data Optimization

Timing optimization following clock tree synthesis (post-CTS) is a crucial step in very large scale integration (VLSI) physical design …

Yuhao Ji, Yuntao Lu, Zuodong Zhang, Zizheng Guo, Yibo Lin, Bei Yu

GPU Acceleration for Versatile Buffer Insertion

With the advancement of circuit design complexity and technology nodes, buffer insertion has become pivotal in mitigating timing …

Yuan Pu, Yuhao Ji, Siying Yu, Zuodong Zhang, Zizheng Guo, Zhuolun He, Yibo Lin, David Pan, Bei Yu

GEM: GPU-Accelerated Emulator-Inspired RTL Simulation

In this paper, we present a GPU-accelerated RTL simulator addressing critical challenges in high-speed circuit verification. …

Zizheng Guo, Yanqing Zhang, Runsheng Wang, Yibo Lin, Haoxing Ren

A Systematic Approach for Multi-Objective Double-Side Clock Tree Synthesis

As the scaling of semiconductor devices nears its limits, utilizing the back-side space of silicon has emerged as a new trend for …

Xun Jiang, Haoran Lu, Yuxuan Zhao, Jiarui Wang, Zizheng Guo, Heng Wu, Bei Yu, Sung Kyu Lim, Runsheng Wang, Ru Huang, Yibo Lin