Zizheng Guo
Zizheng Guo
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PowPrediCT: Cross-Stage Power Prediction with Circuit-Transformation-Aware Learning
Accurate and efficient power analysis at early VLSI design stages is critical for effective power optimization. It is a promising yet …
Yufan Du
,
Zizheng Guo
,
Xun Jiang
,
Zhuomin Chai
,
Yuxiang Zhao
,
Yibo Lin
,
Runsheng Wang
,
Ru Huang
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DOI
Heterogeneous Static Timing Analysis with Advanced Delay Calculator
Static timing analysis (STA) in advanced technology nodes encounter many new challenges in analysis accuracy and speed efficiency. To …
Zizheng Guo
,
Tsung-Wei Huang
,
Zhou Jin
,
Cheng Zhuo
,
Yibo Lin
,
Runsheng Wang
,
Ru Huang
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An Efficient Task-Parallel Pipeline Programming Framework
The pipeline is a fundamental pattern to parallelize a series of stage tasks over a sequence of data in loops. Mainstream pipeline …
Cheng-Hsiang Chiu
,
Zhicheng Xiong
,
Zizheng Guo
,
Tsung-Wei Huang
,
Yibo Lin
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DOI
Accelerating Routability and Timing Optimization with Open-Source AI4EDA Dataset CircuitNet and Heterogeneous Platforms
Routability and timing are two critical metrics for modern VLSI circuits. With increasing design complexity and continuous shrinking of …
Xun Jiang
,
Zizheng Guo
,
Zhuomin Chai
,
Yuxiang Zhao
,
Yibo Lin
,
Runsheng Wang
,
Ru Huang
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DOI
General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism
Gate-level simulation with delay annotation is a both critical and time-consuming task in the circuit design flow. It is highly …
Zizheng Guo
,
Zuodong Zhang
,
Xun Jiang
,
Wuxi Li
,
Yibo Lin
,
Runsheng Wang
,
Ru Huang
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DOI
GPU-Accelerated Rectilinear Steiner Tree Generation
Rectilinear Steiner minimum tree (RSMT) generation is a fundamental component in the VLSI design automation flow. Due to its extensive …
Zizheng Guo
,
Feng Gu
,
Yibo Lin
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DOI
A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction
Fast and accurate pre-routing timing prediction is essential for timing-driven placement since repetitive routing and static timing …
Zizheng Guo
,
Mingjie Liu
,
Jiaqi Gu
,
Shuhan Zhang
,
David Z. Pan
,
Yibo Lin
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DOI
AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Application-based DVAFS
As the timing guardband continues to increase with the continuous technology scaling, better-than-worst-case (BTWC) design has gained …
Zuodong Zhang
,
Zizheng Guo
,
Yibo Lin
,
Runsheng Wang
,
Ru Huang
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DOI
Differentiable-Timing-Driven Global Placement
Placement is critical to the timing closure of the very-large-scale integrated (VLSI) circuit design flow. This paper proposes a …
Zizheng Guo
,
Yibo Lin
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DOI
Efficient Critical Paths Search Algorithm using Mergeable Heap
Path searching is a central step in static timing analysis (STA). State-of-the-art algorithms need to generate path deviations for …
Kexing Zhou
,
Zizheng Guo
,
Tsung-Wei Huang
,
Yibo Lin
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DOI
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