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IncreGPUSTA: GPU-Accelerated Incremental Static Timing Analysis for Iterative Design Flows

Static timing analysis (STA) plays an essential role in VLSI design optimization. While CPU-based incremental STA methods reduce …

Haichuan Liu, Zizheng Guo, Runsheng Wang, Yibo Lin

Differentiable Physical Optimization

Gate sizing and buffer insertion are crucial for VLSI physical optimization; however, conventional decoupled approaches often yield …

Yufan Du, Zizheng Guo, Runsheng Wang, Yibo Lin

DiffCCD: Differentiable Concurrent Clock and Data Optimization

Timing optimization following clock tree synthesis (post-CTS) is a crucial step in very large scale integration (VLSI) physical design …

Yuhao Ji, Yuntao Lu, Zuodong Zhang, Zizheng Guo, Yibo Lin, Bei Yu

GPU Acceleration for Versatile Buffer Insertion

With the advancement of circuit design complexity and technology nodes, buffer insertion has become pivotal in mitigating timing …

Yuan Pu, Yuhao Ji, Siying Yu, Zuodong Zhang, Zizheng Guo, Zhuolun He, Yibo Lin, David Pan, Bei Yu

GEM: GPU-Accelerated Emulator-Inspired RTL Simulation

In this paper, we present a GPU-accelerated RTL simulator addressing critical challenges in high-speed circuit verification. …

Zizheng Guo, Yanqing Zhang, Runsheng Wang, Yibo Lin, Haoxing Ren

A Systematic Approach for Multi-Objective Double-Side Clock Tree Synthesis

As the scaling of semiconductor devices nears its limits, utilizing the back-side space of silicon has emerged as a new trend for …

Xun Jiang, Haoran Lu, Yuxuan Zhao, Jiarui Wang, Zizheng Guo, Heng Wu, Bei Yu, Sung Kyu Lim, Runsheng Wang, Ru Huang, Yibo Lin

Addressing Continuity and Expressivity Limitations in Differentiable Physical Optimization: A Case Study in Gate Sizing

Differentiable optimization is popular for its efficiency and explainability. However, it faces limitations due to its reliance on …

Yufan Du, Zizheng Guo, Yang Hsu, Zhili Xiong, Seunggeun Kim, David Z. Pan, Runsheng Wang, Yibo Lin

Handling Latch Loops in Timing Analysis with Improved Complexity and Divergent Loop Detection

Latch loops introduce feedback cycles in timing graphs for static timing analysis (STA), disrupting timing propagation in topological …

Xizhe Shi, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang

iTAP: An Incremental Task Graph Partitioner for Task-parallel Static Timing Analysis

Recent static timing analysis (STA) tools have utilized task dependency graph (TDG) parallelism to enhance the STA runtime performance. …

Boyang Zhang, Che Chang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yang Sui, Chih-Chun Chang, Yi-Hua Chung, Wan-Luan Lee, Zizheng Guo, Yibo Lin, Tsung-Wei Huang

PathGen: An Efficient Parallel Critical Path Generation Algorithm

Critical Path Generation (CPG) is fundamental for many static timing analysis (STA) applications. As the circuit complexity continues …

Che Chang, Boyang Zhang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yi-Hua Chung, Wan-Luan Lee, Zizheng Guo, Yibo Lin, Tsung-Wei Huang