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HeteroExcept: A CPU-GPU Heterogeneous Algorithm to Accelerate Exception-aware Static Timing Analysis

Static timing analysis (STA) for large-scale modern circuits requires extensive handling of false paths, multi-cycle paths, and other …

Zizheng Guo, Zuodong Zhang, Wuxi Li, Tsung-Wei Huang, Xizhe Shi, Yufan Du, Yibo Lin, Runsheng Wang, Ru Huang

Fusion of Global Placement and Gate Sizing with Differentiable Optimization

Gate sizing is critical in VLSI design because it significantly influences final design quality. Traditional design flows typically …

Yufan Du, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang

HeLEM-GR: Heterogeneous Global Routing with Linearized Exponential Multiplier Method

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Chunyuan Zhao, Zizheng Guo, Rui Wang, Zaiwen Wen, Yun Liang, Yibo Lin

PowPrediCT: Cross-Stage Power Prediction with Circuit-Transformation-Aware Learning

Accurate and efficient power analysis at early VLSI design stages is critical for effective power optimization. It is a promising yet …

Yufan Du, Zizheng Guo, Xun Jiang, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang

Heterogeneous Static Timing Analysis with Advanced Delay Calculator

Static timing analysis (STA) in advanced technology nodes encounter many new challenges in analysis accuracy and speed efficiency. To …

Zizheng Guo, Tsung-Wei Huang, Zhou Jin, Cheng Zhuo, Yibo Lin, Runsheng Wang, Ru Huang

An Efficient Task-Parallel Pipeline Programming Framework

The pipeline is a fundamental pattern to parallelize a series of stage tasks over a sequence of data in loops. Mainstream pipeline …

Cheng-Hsiang Chiu, Zhicheng Xiong, Zizheng Guo, Tsung-Wei Huang, Yibo Lin

Accelerating Routability and Timing Optimization with Open-Source AI4EDA Dataset CircuitNet and Heterogeneous Platforms

Routability and timing are two critical metrics for modern VLSI circuits. With increasing design complexity and continuous shrinking of …

Xun Jiang, Zizheng Guo, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang

General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism

Gate-level simulation with delay annotation is a both critical and time-consuming task in the circuit design flow. It is highly …

Zizheng Guo, Zuodong Zhang, Xun Jiang, Wuxi Li, Yibo Lin, Runsheng Wang, Ru Huang

GPU-Accelerated Rectilinear Steiner Tree Generation

Rectilinear Steiner minimum tree (RSMT) generation is a fundamental component in the VLSI design automation flow. Due to its extensive …

Zizheng Guo, Feng Gu, Yibo Lin

A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction

Fast and accurate pre-routing timing prediction is essential for timing-driven placement since repetitive routing and static timing …

Zizheng Guo, Mingjie Liu, Jiaqi Gu, Shuhan Zhang, David Z. Pan, Yibo Lin