1

GEM: GPU-Accelerated Emulator-Inspired RTL Simulation
In this paper, we present a GPU-accelerated RTL simulator addressing critical challenges in high-speed circuit verification. …
Zizheng Guo, Yanqing Zhang, Runsheng Wang, Yibo Lin, Haoxing Ren
PDF Cite Code
A Systematic Approach for Multi-Objective Double-Side Clock Tree Synthesis
As the scaling of semiconductor devices nears its limits, utilizing the back-side space of silicon has emerged as a new trend for …
Xun Jiang, Haoran Lu, Yuxuan Zhao, Jiarui Wang, Zizheng Guo, Heng Wu, Bei Yu, Sung Kyu Lim, Runsheng Wang, Ru Huang, Yibo Lin
Cite Arxiv
Addressing Continuity and Expressivity Limitations in Differentiable Physical Optimization: A Case Study in Gate Sizing
Differentiable optimization is popular for its efficiency and explainability. However, it faces limitations due to its reliance on …
Yufan Du, Zizheng Guo, Yang Hsu, Zhili Xiong, Seunggeun Kim, David Z. Pan, Runsheng Wang, Yibo Lin
PDF Cite
Handling Latch Loops in Timing Analysis with Improved Complexity and Divergent Loop Detection
Latch loops introduce feedback cycles in timing graphs for static timing analysis (STA), disrupting timing propagation in topological …
Xizhe Shi, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang
PDF Cite
iTAP: An Incremental Task Graph Partitioner for Task-parallel Static Timing Analysis
Recent static timing analysis (STA) tools have utilized task dependency graph (TDG) parallelism to enhance the STA runtime performance. …
Boyang Zhang, Che Chang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yang Sui, Chih-Chun Chang, Yi-Hua Chung, Wan Luan Lee, Zizheng Guo, Yibo Lin, Tsung-Wei Huang
Cite DOI
PathGen: An Efficient Parallel Critical Path Generation Algorithm
Critical Path Generation (CPG) is fundamental for many static timing analysis (STA) applications. As the circuit complexity continues …
Che Chang, Boyang Zhang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yi-Hua Chung, Wan Luan Lee, Zizheng Guo, Yibo Lin, Tsung-Wei Huang
Cite DOI
HeteroExcept: A CPU-GPU Heterogeneous Algorithm to Accelerate Exception-aware Static Timing Analysis
Static timing analysis (STA) for large-scale modern circuits requires extensive handling of false paths, multi-cycle paths, and other …
Zizheng Guo, Zuodong Zhang, Wuxi Li, Tsung-Wei Huang, Xizhe Shi, Yufan Du, Yibo Lin, Runsheng Wang, Ru Huang
PDF Cite DOI
Fusion of Global Placement and Gate Sizing with Differentiable Optimization
Gate sizing is critical in VLSI design because it significantly influences final design quality. Traditional design flows typically …
Yufan Du, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang
PDF Cite DOI
HeLEM-GR: Heterogeneous Global Routing with Linearized Exponential Multiplier Method
Add the full text or supplementary notes for the publication here using Markdown formatting.
Chunyuan Zhao, Zizheng Guo, Rui Wang, Zaiwen Wen, Yun Liang, Yibo Lin
PDF Cite DOI
PowPrediCT: Cross-Stage Power Prediction with Circuit-Transformation-Aware Learning
Accurate and efficient power analysis at early VLSI design stages is critical for effective power optimization. It is a promising yet …
Yufan Du, Zizheng Guo, Xun Jiang, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang
PDF Cite DOI