Best Paper Nomination

GEM: GPU-Accelerated Emulator-Inspired RTL Simulation
In this paper, we present a GPU-accelerated RTL simulator addressing critical challenges in high-speed circuit verification. …
Zizheng Guo, Yanqing Zhang, Runsheng Wang, Yibo Lin, Haoxing Ren
PDF Cite Code
PathGen: An Efficient Parallel Critical Path Generation Algorithm
Critical Path Generation (CPG) is fundamental for many static timing analysis (STA) applications. As the circuit complexity continues …
Che Chang, Boyang Zhang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yi-Hua Chung, Wan Luan Lee, Zizheng Guo, Yibo Lin, Tsung-Wei Huang
Cite DOI
Fusion of Global Placement and Gate Sizing with Differentiable Optimization
Gate sizing is critical in VLSI design because it significantly influences final design quality. Traditional design flows typically …
Yufan Du, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang
PDF Cite DOI