Analyzing Timing in Shorter Time: A Journey Through Heterogeneous Parallelism for Static Timing Analysis

Abstract

This paper reviews recent work on the acceleration of static timing analysis (STA), with a special focus on parallel and heterogeneous computing techniques. Timing analysis is one of the most critical tasks in circuit design. The ever-increasing size and complexity of modern circuit design has asked for unprecedented STA runtime speedup which has to be achieved through CPU-GPU heterogeneous computing. GPU-accelerated STA is however difficult due to its nature of irregular computation and memory access patterns. We demonstrate and analyze the algorithm design and scheduling considerations in recent works targeting various different STA stages, and discuss future directions of STA acceleration as well as the future of timing optimization in heterogeneous circuit design flow.