Design for reliability in advanced technology nodes has become increasingly challenging and requires comprehensive support from aging-aware EDA tools and optimization flows. This paper summarizes recent cross-layer aging-aware design studies from an EDA perspective, overviews advances in device-level reliability modeling together with circuit- and system-level aging-aware analysis frameworks, and shows that the cross-layer framework enables more accurate analysis to reduce over-design, optimize PPA across lifetime, and support efficient exploration of error-resilient architectures.